1. Field of the Invention
The present invention relates to a data transmission circuit, and more particularly, to a data recovery circuit and method for reducing power consumption and minimizing errors due to clock skew by performing non-integer times oversampling sampling.
2. Description of the Related Art
In most present image processing systems, data is processed in a digital region and an interface between systems uses an analog signal that is simple to implement. However, the interface using an analog signal has a drawback of limited accuracy due to noise between signals and other analog errors. To solve this problem, it is more efficient to directly transmit a digital signal.
Generally, in a data transmission system for transmitting predetermined data, a method using parallel data channels is widely used for digitally interfacing between systems. However, as the number of data transmission channels increases, the method using parallel data channels may suffer from problems. For this reason, a recent trend is to use serial transmission instead of parallel transmission.
The method using serial transmission channels has an advantage over the method using parallel transmission channels in that fewer channels are used. However, in most cases, if data is transmitted using serial transmission channels, a high-speed serial signal should be recovered to a parallel data signal at the receiving end. At this time, when serial data is recovered to a parallel data format, data recovery may be difficult due to clock skew at the receiving end.
To solve this problem, in conventional technology, a bit section of a received signal is two or three times oversampled and data having a high frequency is determined as actual data. However, the two times oversampling has a drawback of lower accuracy, and the three times oversampling has a drawback in that it is difficult to implement a circuit for generating high-speed clock signals.